An interleaving device is, in particular, located between a channel encoding device and a modulator device. In the same way, a de-interleaving device is located between a demodulator device and a channel decoding device. Interleaving is scrambling the processing order to break up neighborhood-relations in successive data samples, and de-interleaving brings them into the original sequences again. Channel de-interleaving is a memory intensive operation which is among the most energy usage operations in digital high-throughput receivers. There are two standard channel interleaving and de-interleaving techniques commonly referred as “block” and “convolutional”.
The invention is more particularly directed to block interleavers which are used in various cellular systems, for example in 3GPP or IS-95. State-of-the-art implementations use a single large physical memory for de-interleaving, and suffer high energy dissipation due to numerous sample-wide accesses to the large memory, where one sample is composed of several bits.
Moreover, block de-interleaving results in memory spaces with long storage-lifetimes which drastically limits continuous memory re-use. As a result, large adaptation buffers are required that further increases the area of the circuit and the energy dissipation. So, in conventional de-interleaving approaches, this memory intensive operation is both power consuming due to frequent accesses to large memories and area inefficient due to large adaptation buffers.